// TOP_tb

module TOP_tb ();
    
    reg clk,rst_n;
    wire V;
    
    TOP U1(
    .clk(clk),
    .rst_n(rst_n),
    .V(V)
    );
    
    initial begin
        clk = 0;
        rst_n = 1;
        
        #10 rst_n = 0;
        #20 rst_n = 1;
        
        #5000 $stop;
    end
    
    always #5 clk = ~clk;
    
endmodule //TOP_tb
